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www.irf.com ? 2008 international rectifier 31 may, 2011 irs21867s high and low side driver features ? floating channel designed for bootstrap operation ? fully operational to +600v ? tolerant to negative transient voltage, dv/dt immune ? low vcc operation ? gate drive supply range from 5v to 20v ? undervoltage lockout for both channels ? 3.3v and 5v input logic compatible ? matched propagation delay for both channels ? logic and power ground +/ 5v offset ? lower di/dt gate driver for better noise immunity ? output source/sink current capability 4.0a (typ.) ? leadfree, rohs compliant applications ? battery powered equipment ? handtools ? forklifts ? golfcarts ? rc hobby equipment ? ebike product summary topology singlephase v offset 600v v out 10v C 20v i o+ & i o (typical) 4.0a & 4.0a t on & t off (typical) 170ns & 170ns package options soic8 typical connection diagram irs21867s refer to lead assignment for correct pin configuration. this diagrams show electrical connections only. please refer to our application notes and design tips for proper circuit board layout irs21867s refer to lead assignment for correct pin configuration. this diagrams show electrical connections only. please refer to our application notes and design tips for proper circuit board layout
irs21867s www.irf.com ? 2010 international rectifier 2 table of contents page typical connection diagram 1 description/feature comparison 3 qualification information 3 absolute maximum ratings 4 recommended operating conditions 4 dynamic electrical characteristics 5 static electrical characteristics 5 functional block diagram 6 input/output pin equivalent circuit diagram 7 lead definitions 8 lead assignments 8 application information and additional details 9 package details 17 tape and reel details 18 part marking information 19 ordering information 20
irs21867s www.irf.com ? 2010 international rectifier 3 description the irs21867 is a high voltage, high speed power mo sfet and igbt driver with independent high and low side referenced output channels. proprietary hvic a nd latch immune cmos technologies enable ruggedized monolithic construction. low vcc operation allows u se in battery powered applications. the logic input is compatible with standard cmos or lsttl output, down to 3.3 v logic. the output drivers feature a high pulse current buffer stage designed for minimum dri ver crossconduction. the floating channel can be u sed to drive an nchannel power mosfet or igbt in the h ighside configuration which operates up to 600v. qualification information ? industrial ?? qualification level comments: this family of ics has passed jedecs industrial qualification. irs consumer qualificat ion level is granted by extension of the higher industrial level . moisture sensitivity level soic8n msl2 ??? 260c (per ipc/jedec jstd020) machine model class a (per jedec standard jesd22a115) esd human body model class 2 (per eia/jedec standard eia/jesd22a114) ic latchup test class i, level a (per jesd78) rohs compliant yes ? qualification standards can be found at internation al rectifiers web site http://www.irf.com/ ?? higher qualification ratings may be available shoul d the user have such requirements. please contact your international rectifier sales representative f or further information. ??? higher msl ratings may be available for the specifi c package types listed here. please contact your international rectifier sales representative for fu rther information.
irs21867s www.irf.com ? 2010 international rectifier 4 absolute maximum ratings absolute maximum ratings indicate sustained limits beyond which damage to the device may occur. all voltage parameters are absolute voltages referenced to com. the thermal resistance and power dissipati on ratings are measured under board mounted and still air conditions. note 1: all supplies are fully tested at 25v. recommended operating conditions for proper operation the device should be used with in the recommended conditions. all voltage paramete rs are absolute voltages referenced to com. the v s offset rating is tested with all supplies biased a t (vcc com) = 15v. ? note 2: logic operational for v s of 5v to +600v. logic state held for v s of 5v to Cv bs . (please refer to the design tip dt973 for more details). symbol definition min max units v b high side floating absolute voltage 0.3 625 (note 1) v s high side floating supply offset voltage v b C 25 v b + 0.3 v ho high side floating output voltage v s 0.3 v b + 0.3 v cc low side and logic fixed supply voltage 0.3 25 (n ote 1) v lo low side output voltage 0.3 v cc + 0.3 v in logic input voltage (hin & lin) com 0.3 v cc + 0.3 v dv s /dt allowable offset supply voltage transient 50 v/ns p d package power dissipation @ ta 25c 0.625 w rth ja thermal resistance, junction to ambient 200 c/w t j junction temperature 150 t s storage temperature 50 150 t l lead temperature (soldering, 10 seconds) 300 c symbol definition min max units v b high side floating supply absolute voltage v s + 10 v s + 20 v s high side floating supply offset voltage note 2 600 v ho high side floating output voltage v s v b v cc low side and logic fixed supply voltage 10 20 v lo low side output voltage 0 v cc v in logic input voltage (hin & lin) com v cc v t a ambient temperature 40 125 c
irs21867s www.irf.com ? 2010 international rectifier 5 dynamic electrical characteristics v cc = v bs = 15v, c l = 1000 pf, t a = 25c unless otherwise specified. symbol definition min typ max units test conditions t on turnon propagation delay 170 250 v s = 0v t off turnoff propagation delay 170 250 v s = 0v or 600v mt delay matching | t on C t off | 35 t r turnon rise time 22 38 t f turnoff fall time 18 30 ns v s = 0v static electrical characteristics v cc = v bs = 15v,, and t a = 25c unless otherwise specified. the v in , and i in parameters are referenced to com and are applicable to the respective input lead s: hin, and lin. the v o , and i o parameters are referenced to v s /com and are applicable to the respective output le ads: ho and lo. symbol definition min typ max units test conditions v ih logic 1 input voltage for ho & lo 2.5 v il logic 0 input voltage for ho & lo 0.8 v cc = 10v to 20v v oh high level output voltage, v cc or v bs v o 1.4 i o = 0ma v ol low level output voltage, v o 0.15 v i o = 20ma i lk offset supply leakage current 50 v b = v s = 600 v i qbs quiescent v bs supply current 20 60 150 i qcc quiescent v cc supply current 50 120 240 v in = 0v or 5v i in+ logic 1 input bias current 250 hin = lin = 5 v i in logic 0 input bias current 5.0 a hin = lin = 0v v ccuv+ v bsuv+ v cc and v bs supply undervoltage positive going threshold 5.34 6 6.66 v ccuv v bsuv v cc and v bs supply undervoltage negative going threshold 4.90 5.50 6.10 v ccuvh v bsuvh v cc and v bs supply undervoltage hysteresis 0.5 v i o+ output high short circuit pulsed current 4.0 v o = 0v, pw 10s i o output low short circuit pulsed current 4.0 a v o = 15v, pw 10s
irs21867s www.irf.com ? 2010 international rectifier 6 irs21867 irs21867 functional block diagrams
irs21867s www.irf.com ? 2010 international rectifier 7 input/output pin equivalent circuit diagrams v cc com/v ss lo esd diode esd diode v b v s ho esd diode esd diode 25v 25v 600v com v cc com/v ss lo esd diode esd diode v b v s ho esd diode esd diode 25v 25v 600v com com com
irs21867s www.irf.com ? 2010 international rectifier 8 lead definitions: irs21867s pin# symbol description 1 v cc lowside and logic fixed supply 2 hin logic input for highside gate driver output (ho), in phase with ho 3 lin logic input for lowside gate driver output (lo), i n phase with lo 4 com lowside return 5 lo lowside gate drive output 6 v s highside floating supply return 7 ho highside gate drive output 8 v b highside floating supply lead assignments 8 lead soic irs21867s
irs21867s www.irf.com ? 2010 international rectifier 9 application information and additional details informations regarding the following topics are inc luded as subsections within this section of the dat asheet. ? igbt/mosfet gate drive ? switching and timing relationships ? matched propagation delays ? input logic compatibility ? undervoltage lockout protection ? negative v s transient soa ? pcb layout tips ? additional documentation igbt/mosfet gate drive the irs21867 hvic is designed to drive mosfet or ig bt power devices. figures 1 and 2 illustrate sever al parameters associated with the gate drive functiona lity of the hvic. the output current of the hvic, used to drive the gate of the power switch, is defined as i o . the voltage that drives the gate of the external power switch is defined as v ho for the highside power switch and v lo for the lowside power switch; this parameter is s ometimes generically called v out and in this case does not differentiate between th e highside or lowside output voltage. v s (or com) ho (or lo) v b (or v cc ) i o+ v ho (or v lo ) + v s (or com) ho (or lo) v b (or v cc ) i o figure 1: hvic sourcing current figure 2: hvic sinking current
irs21867s www.irf.com ? 2010 international rectifier 10 switching and timing relationships the relationships between the input and output sign als of the irs21867 are illustrated below in figure s 3, 4. from these figures, we can see the definitions of severa l timing parameters (i.e., pw in , pw out , t on , t off , t r , and t f ) associated with this device. linx (or hinx) 50% 50% pw in pw out 10% 10% 90% 90% t off t on t r t f lox (or hox) figure 3: switching time waveforms figure 4: input/output timing diagram matched propagation delays the irs21867 is designed with propagation delay mat ching circuitry. with this feature, the ics respo nse at the output to a signal at the input requires approximat ely the same time duration (i.e., t on , t off ) for both the lowside channels and the highside channels; the maximum di fference is specified by the delay matching paramet er (mt). the propagation turnon delay (t on ) is matched to the propagation turnon delay (t off ).
irs21867s www.irf.com ? 2010 international rectifier 11 figure 5: delay matching waveform definition input logic compatibility the inputs of this ic are compatible with standard cmos and ttl outputs. the irs21867 has been design ed to be compatible with 3.3 v and 5 v logiclevel signals. figure 8 illustrates an input signal to the irs228 67, its input threshold values, and the logic state of the ic as a result of the input signal. input signal (irs23364d) v ih v il input logic level high low low figure 6: hin & lin input thresholds
irs21867s www.irf.com ? 2010 international rectifier 12 undervoltage lockout protection this ic provides undervoltage lockout protection on both the v cc (logic and lowside circuitry) power supply and th e v bs (highside circuitry) power supply. figure 7 is u sed to illustrate this concept; v cc (or v bs ) is plotted over time and as the waveform crosses the uvlo threshold (v ccuv+/ or v bsuv+/ ) the undervoltage protection is enabled or disable d. upon powerup, should the v cc voltage fail to reach the v ccuv+ threshold, the ic will not turnon. additionally, if the v cc voltage decreases below the v ccuv threshold during operation, the undervoltage locko ut circuitry will recognize a fault condition and shutdown the high and lowside gate drive outputs. upon powerup, should the v bs voltage fail to reach the v bsuv threshold, the ic will not turnon. additionally, if the v bs voltage decreases below the v bsuv threshold during operation, the undervoltage locko ut circuitry will recognize a fault condition, and shutdown the highside gate dr ive outputs of the ic. the uvlo protection ensures that the ic drives the external power devices only when the gate supply vo ltage is sufficient to fully enhance the power devices. wit hout this feature, the gates of the external power switch could be driven with a low voltage, resulting in the power s witch conducting current while the channel impedanc e is high; this could result in very high conduction losses within the power device and could lead to power device fai lure. figure 7: uvlo protection
irs21867s www.irf.com ? 2010 international rectifier 13 tolerant to negative v s transients a common problem in todays highpower switching co nverters is the transient response of the switch no des voltage as the power switches transition on and off quickly while carrying a large current. a typical 3phase inverter circuit is shown in figure 8; here we define the power switche s and diodes of the inverter. if the highside switch (e.g., the igbt q1 in figur es 9 and 10) switches off, while the u phase curren t is flowing to an inductive load, a current commutation occurs from h ighside switch (q1) to the diode (d2) in parallel with the lowside switch of the same inverter leg. at the same insta nce, the voltage node v s1 , swings from the positive dc bus voltage to the negative dc bus voltage. figure 8: three phase inverter q1 on d2 v s1 q2 off i u dc+ bus dc bus figure 9: q1 conducting figure 10: d2 conducting also when the v phase current flows from the induct ive load back to the inverter (see figures 11 and 1 2), and q4 igbt switches on, the current commutation occurs fr om d3 to q4. at the same instance, the voltage node , v s2 , swings from the positive dc bus voltage to the nega tive dc bus voltage.
irs21867s www.irf.com ? 2010 international rectifier 14 figure 11: d3 conducting figure 12: q4 conducting however, in a real inverter circuit, the v s voltage swing does not stop at the level of the ne gative dc bus, rather it swings below the level of the negative dc bus. this undershoot voltage is called negative v s transient. the circuit shown in figure 13 depicts one leg of t he three phase inverter; figures 14 and 15 show a s implified illustration of the commutation of the current betw een q1 and d2. the parasitic inductances in the pow er circuit from the die bonding to the pcb tracks are lumped togeth er in l c and l e for each igbt. when the highside switch is on, v s1 is below the dc+ voltage by the voltage drops asso ciated with the power switch and the parasitic elem ents of the circuit. when the highside power switch turns off , the load current momentarily flows in the lowsid e freewheeling diode due to the inductive load connected to v s1 (the load is not shown in these figures). this cu rrent flows from the dc bus (which is connected to the com pin of the h vic) to the load and a negative voltage between v s1 and the dc bus is induced (i.e., the com pin of the hvic i s at a higher potential than the v s pin). figure 13: parasitic elements figure 14: v s positive figure 15: v s negative in a typical motor drive system, dv/dt is typically designed to be in the range of 35 v/ns. the negat ive v s transient voltage can exceed this range during some events su ch as short circuit and overcurrent shutdown, when di/dt is greater than in normal operation. international rectifiers hvics have been designed for the robustness required in many of todays dema nding applications. an indication of the irs21867s robus tness can be seen in figure 16, where there is repr esented the irs2607 safe operating area at v bs =15v based on repetitive negative v s spikes. a negative v s transient voltage falling in the grey area (outside soa) may lead to ic permanent damage; viceversa unwanted functional anomalies or permanent damage to the ic do not appear if nega tive vs transients fall inside soa.
irs21867s www.irf.com ? 2010 international rectifier 15 figure 16: negative v s transient soa for irs2607 @ vbs=15v even though the irs21867 has been shown able to han dle these large negative v s transient conditions, it is highly recommended that the circuit designer always limit the negative v s transients as much as possible by careful pcb layout and component use. pcb layout tips distance between high and low voltage components: its strongly recommended to place the components tied to the floating voltage pins (v b and v s ) near the respective high voltage portions of the device. please see the case outline information in this datasheet for the detai ls. ground plane: in order to minimize noise coupling, the ground pl ane should not be placed under or near the high voltage floating side. gate drive loops: current loops behave like antennas and are able to receive and transmit em noise (see figure 17). in order to reduce the em coupling and improve the power switch turn on/off performance, t he gate drive loops must be reduced as much as possibl e. moreover, current can be injected inside the gat e drive loop via the igbt collectortogate parasitic capacitance. the parasitic autoinductance of the gate loop contributes to developing a voltage across the gateemitter, thus increasing the possibility of a self turnon effect.
irs21867s www.irf.com ? 2010 international rectifier 16 figure 17: antenna loops supply capacitor: it is recommended to place a bypass capacitor (c in ) between the v cc and com pins. a ceramic 1 f ceramic capacitor is suitable for most applications. this component should be placed as close as possible to the pins in order to reduce parasiti c elements. routing and placement: power stage pcb parasitic elements can contribute to large negative voltage transients at the switch node; it is recommended to limit the phase voltage negative transients. in o rder to avoid such conditions, it is recommended to 1) mini mize the highside emitter to lowside collector di stance, and 2) minimize the lowside emitter to negative bu s rail stray inductance. however, where negative v s spikes remain excessive, further steps may be taken to reduce the spike. this includes placing a resi stor (5 or less) between the v s pin and the switch node (see figure 18), and in so me cases using a clamping diode between com and v s (see figure 19). see dt044 at www.irf.com for more detailed information. figure 18: v s resistor figure 19: v s clamping diode additional documentation several technical documents related to the use of h vics are available at www.irf.com ; use the site search function and the document number to quickly locate them. below is a short list of some of these docum ents. dt973: managing transients in control ic driven po wer stages dt044: using monolithic high voltage gate drivers an978: hv floating mosgate driver ics
irs21867s www.irf.com ? 2010 international rectifier 17 package details: soic8n
irs21867s www.irf.com ? 2010 international rectifier 18 tape and reel details: soic8n e f a c d g a b h note : controlling dim ension in m m loaded tape feed direction a h f e g d b c carrier tape dimension for 8soicn code min max min max a 7.90 8.10 0.311 0.318 b 3.90 4.10 0.153 0.161 c 11.70 12.30 0.46 0.484 d 5.45 5.55 0.214 0.218 e 6.30 6.50 0.248 0.255 f 5.10 5.30 0.200 0.208 g 1.50 n/a 0.059 n/a h 1.50 1.60 0.059 0.062 metric imperial reel dimensions for 8soicn code min max min max a 329.60 330.25 12.976 13.001 b 20.95 21.45 0.824 0.844 c 12.80 13.20 0.503 0.519 d 1.95 2.45 0.767 0.096 e 98.00 102.00 3.858 4.015 f n/a 18.40 n/a 0.724 g 14.50 17.10 0.570 0.673 h 12.40 14.40 0.488 0.566 metric imperial
irs21867s www.irf.com ? 2010 international rectifier 19 part marking information
irs21867s www.irf.com ? 2010 international rectifier 20 ordering information p/n package packing pcs IRS21867SPBF soic8 tube 95 irs21867strpbf soic8 tape & reel 2500
irs21867s www.irf.com ? 2010 international rectifier 21 the information provided in this document is believ ed to be accurate and reliable. however, internatio nal rectifier assumes no responsibility for the consequences of the use of t his information. international rectifier assumes n o responsibility for any infringement of patents or of other rights of third parties which may result from the use of this info rmation. no license is granted by implication or otherwise under any patent or patent rights of international rectifier. the specificat ions mentioned in this document are subject to change without notice. this document su persedes and replaces all information previously su pplied. for technical support, please contact irs technica l assistance center http://www.irf.com/technicalinfo/ world headquarters: 233 kansas st., el segundo, california 90245 tel: (310) 2527105 revision history date comment 5/20/2010 initial draft 6/10/2010 changed abs max to 25v, updated iin+ to 250ua(typ) to reflect 20kohm pulld own, removed min spec (2a) from io+/io, updated block diagram based on irs2188 d/s 03/30/2011 add recommended operation condition note 05/27/2011 add esd and latch up specs 05/31/2011 add application info and ordering info

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